Multi-standard data communication interface circuitry for programmable logic devices

[0006]The aligned bytes and output signals of the hard IP circuitry performing checks of the aligned bytes as described in the preceding paragraph are applied to downstream circuitry. This downstream circuitry may include additional dedicated data processing circuitry in the hard IP portion of the PLD. The downstream circuitry also includes the programmable logic portion of the PLD. That programmable logic is typically configured (programmed) to perform tasks on the aligned bytes that tend to have relatively large variation among a wide range of communication protocols that can be implemented by the PLD. For example, these tasks typically include synchronizing the bytes in accordance with the data structure of whatever communication protocol is being implemented. As part of its tasks, the programmable logic may feed back to the hard IP signals for affecting how the bytes are being aligned in the hard IP. To increase the speed at which a change in byte alignment can be made, the programmable logic can enable the byte alignment circuitry in the hard IP to respond directly to code or CRD errors detected far upstream in the hard IP as described in the preceding paragraph. The hard IP preferably operates on two bytes at a time.

This is made more difficult by both of the trends noted above, i.e., increased communication speed and increased number of possible communication protocols.

However, increased number of possible protocols suggests that a large amount of dedicated circuitry will be needed (to support the peculiarities of each possible protocol), but that much of that circuitry will be unused and therefore wasted when the PLD is used for only one or at most a few of the possible protocols.