Method and system of cycle slip framing in a deserializer

a technology of serial bit data and frame, applied in pulse generators, pulse manipulation, pulse techniques, etc., can solve problems such as unfavorable system effects, circuits not “correct-by-design”, and inability to perfectly synchronize both inputs

Active Publication Date: 2008-05-13
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented technology allows receivers to perform cyclic slipping on data streams without any errors or issues caused by timing differences between different parts of the stream's transmission path. It also prevents glitching when there may have been problems during this process due to incorrect signals being sent over multiple paths simultaneously. Additionally, it can achieve faster processing times compared to traditional methods like phase locked loops (PLL) which use more complex logic components than usual but still works well enough at high speeds.

Problems solved by technology

The technical problem addressed in this patents relating to improving the performance of digital receivers has been finding ways to improve their reception capabilities without increasing processing requirements beyond what they were previously possible due to limited bandwidth resources available within analog receiving channels. Existing methods have limitations including requiring multiple cycles before resolving any errors caused during transmission. Additionally, existing techniques require complex logic blocks and may introduce unreliabilities like incorrect decisions leading to unnecessary actions.

Method used

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  • Method and system of cycle slip framing in a deserializer
  • Method and system of cycle slip framing in a deserializer
  • Method and system of cycle slip framing in a deserializer

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Embodiment Construction

[0026]Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscu

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Abstract

A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.

Description

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Claims

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Application Information

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Owner TAIWAN SEMICON MFG CO LTD
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