4 results about "Netlist" patented technology

Various methods and apparatuses (such as computer readable media implementing the method) are described that relate to proximate placement of sequential cells of an integrated circuit netlist. For example, the preliminary placement is received; and based on the preliminary placement, a group of sequential cells is identified as being subject to improved power and/or timing upon subsequent placement. In another example, identification is received of a group of sequential cells subject to improved power and/or timing upon subsequent placement; and proximate placement is performed of the identified group of sequential cells. In yet another example, a proximate arrangement of a group of sequential cells is received; and if proximate placement fails, then the group of sequential cells is disbanded and placement is performed of the sequential cells of the disbanded group.

System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.

The invention discloses a layout method of an FPGA with a multi-bare-chip structure and relates to the technical field of FPGA. The method comprises the following steps of: cutting a large user inputnetlist into a plurality of small sub-netlists; each bare chip is ensured to have enough resources to carry out layout on each small subnet list; fixing the positions of all IO ports; selecting a connection point and a virtual stress application point on the bare chips according to the connection relationship between the bare chips and the connection relationship between the subnet lists; carryingout single-bare-chip layout on each bare chip based on the traction effect of the virtual stress application points on the bare chips on the corresponding connection points and the traction effect ofthe IO ports at the specified positions; the plurality of bare chips are arranged separately; in the layout method, the points with the connection relationship between the bare chips are dragged close to one direction, so that the purpose of optimizing the connection relationship between the bare chips is achieved, and the layout method provides a technical basis for a method for realizing large-scale and large-area FPGA chips by cascading a plurality of small-scale and small-area bare chips so as to meet large logic resource requirements.