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Reconfigurable microprocessor hardware architecture,Method, system and device for compiling AI chip and medium,Data encryption system and method

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In engineering, hardware architecture refers to the identification of a system's physical components and their interrelationships. This description, often called a hardware design model, allows hardware designers to understand how their components fit into a system architecture and provides to software component designers important information needed for software development and integration. Clear definition of a hardware architecture allows the various traditional engineering disciplines (e.g., electrical and mechanical engineering) to work more effectively together to develop and manufacture new machines, devices and components.

Reconfigurable microprocessor hardware architecture

ActiveUS20170300333A1Reduce operational latencyEfficient programmingCAD circuit designArchitecture with single central processing unitSelf routingMemory interface

A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, a Time Field is added to the instruction format for all programming units that specifies the number of clock cycles for which only one instruction fetch and decode will be performed.

Owner:WANG XIAOLIN +1

Method, system and device for compiling AI chip and medium

InactiveCN112232497ASolve interface problemsComprehensive and reliable quantification functionsPhysical realisationCode compilationHardware architectureAlgorithm

The invention discloses a method, system and device for compiling an AI chip and a storage medium, and the method comprises the steps of carrying out the quantification of a network model of the AI chip, and carrying out the precision adjustment of the quantified network model based on the weight of the network model; allocating calculation of the convolutional neural network to different MAC calculation units of the AI chip in the network model after precision adjustment so as to optimize a calculation process of the network model; and acquiring hardware architecture parameters, and generating a continuous calculation flow according to the hardware architecture parameters and the network model. According to the invention, the AI chip is quantified and the precision is adjusted, so that the performance is more perfect; the calculation of the network is optimized to the maximum extent, the calculation steps are reduced, and the utilization rate of the MAC calculation unit is maximized;the utilization rate of the AI equipment is improved by generating the calculation flow capable of enabling the calculation equipment to be always in the busy state in the network reasoning process.