Reconfigurable microprocessor hardware architecture
a hardware architecture and microprocessor technology, applied in the field of microprocessor designs and programming methods, can solve the problems of gpm-based solutions being generally more expensive and power hungry than gpm-based solutions, and only offering very limited programmability, so as to reduce the overall operation delay
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[0086]As explained in more detail above, present-day single-core processors uses a variety of different methods in an attempt to optimize their efficiency in executing certain specific software programs. However, due to the fundamental limitations of a pipelined architecture, when one aspect is optimized, other aspects cannot be simultaneously optimized, resulting in inefficient SoC designs that include large number of cores with different architectures. As a result, present day multi-core processors have very low efficiency because of their necessarily poor data synchronization.
[0087]Underlying embodiments of the present invention as disclosed herein is a very different strategy for improving both single-core efficiency and multi-core efficiency. First, a cognitive data routing network is used to allow any operations to execute either in series or in parallel in any order, thereby improving the efficiency of the programmable processing units. Second, the processing units can be pro...
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