A non-volatile memory includes an array (30) of cells in rows and columns (311-316; 331-336),where the cells of each column (311-316; 331-336) are positioned within a respective isolated p-well region (301, 302, 303). Control gates of sequential memory cells in rows of the array (311, 321, 331; 316, 316, 336) are electrically coupled by common wordlines (3071, 3072 3076). Bitlines (3091, 3092, 3093) electrically couple drain or source regions of each memory cell in the respective columns (311-316; 331-336). The source lines (3051, 3052, 3053) and at least one memory cell in each column of the array (311-316; 331-336) are electrically coupled to the p-well region (301, 302, 303) corresponding to the column of the source line and cell. Each column of the array (30) is therefore located within an isolated well.