Non-volatile memory, method of manufacture, and method of programming

[0024] According to one embodiment of the invention, a nonvolatile memory (NVM) array, such as an Electrically Erasable Programmable Read Only Memory (EEPROM) array, includes columns of memory cells formed in separate p-well regions to The programming threshold voltage distribution width of selected memory cells in the array is reduced. For example, multiple memory cells sharing a common bit line are formed within a well region such as a p-well region. In one embodiment, each isolated p-well forms a column of memory cells in the array. The p-wells are electrically isolated from each other using shallow trench isolation (STI) structures. Memory cells formed in individual p-well regions share a common bit line and a common source line. Isolating the memory array into individual p-wells improves programming control by allowing the memory cells of the array to be programmed into a tight threshold voltage distribution.

[0025] refer to image 3 , the memory cell array 30 includes