6 results about "Memory array" patented technology

An electronic system includes a three terminal device having a light emitting portion and a magnetically sensitive portion. The magnetically sensitive portion is for modulating light emission from the light emitting portion. The device is a spin valve transistor having a light-emitting quantum well in its collector. The device can convert a magnetic digital signal to both an electrical digital signal and an optical digital signal, wherein either or both of these signals can be provided as a device output. The magnetically sensitive portion of the device is formed of a pair of magnetically permeable layers. When the layers are aligned electron current can pass through with sufficient energy to reach a quantum well where they recombine, generating light. The device may be used to read a magnetic storage medium, such as a disk drive. Or it can be used to provide a display or a memory array composed of single device magnetic write, optical read memory cells. Amplification can be provided to the transistor by adjusting the collector base voltage to provide secondary electrons by impact ionization to provide greater electron current and a correspondingly larger optical emission signal.

A cross point memory array includes a structure in which holes are formed in an insulating layer and a storage node is formed in each of the holes. The storage node may include a memory resistor and a switching structure. The master for an imprint process used to form the cross-point memory array includes various pattern shapes, and the method of manufacturing the master uses various etching methods.

A multi-port memory array according to some embodiments of the present invention includes a first complementary pair of bit lines of length L corresponding to a first port; a second complementary pair of bit lines of length L corresponding to a second port, wherein the first complementary pair of bit lines is interleaved with the second complementary pair of bit lines, and wherein the first complementary pair of bit lines is twisted at L/2 and the second complementary pair of bit lines is twisted at L/4 and 3L/4. The capacitive coupling between a bit line of the first complementary pair of bit lines and each of the bit lines of the second complementary pair of bit lines is therefore the same, resulting in an elimination of the effects of capacitive coupling.

A memory device includes a memory array and a frequency-to-voltage converter. The memory array includes a plurality of memory cells arranged in rows and columns, and gates of the memory cells in the same row are coupled to each other and connected to a word line. The frequency-to-voltage converter coupled between the word line and a clock signal source outside the memory device receives a clock signal, and correspondingly outputs different voltages to the word line in accordance with the frequency of the clock signal.