DLL circuit

a delay lock and circuit technology, applied in the direction of digital storage, generating/distributing signals, instruments, etc., can solve the problems of reducing current consumption, reducing power consumption, and difficulty in generating timing other than one cycle or half cycle unit of reference clock signals, so as to reduce power consumption

Inactive Publication Date: 2006-03-28
LONGITUDE SEMICON S A R L
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0015]Accordingly, it is an object of the invention to provide a DLL circuit which can automatically vary the current value of the constant-current source in each incorporated differential amplifier circuit according to the frequency of input signals and can reduce power consumption according to the frequency of input signals over a wide range of frequencies of input signals.

Problems solved by technology

This makes it difficult to generate timing other than one cycle or half cycle unit of the reference clock signal.
The DLL circuits, which control the phase in an analog manner, however, involve a problem that lowering the operating frequency does not reduce current consumption.
Therefore, lowering the operating frequency results in lowered current consumption.
The conventional DLL circuits, however, do not have any means which can automatically vary the current value of the constant-current source in each incorporated differential amplifier circuit according to the operating speed (frequency of signal input into DLL circuit).
Therefore, an attempt to use the conventional DLL circuit, which can cope with a high input signal frequency, also in the case of a low input signal frequency poses a problem or wasteful power consumption.

Method used

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Examples

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Embodiment Construction

[0044]Preferred embodiments of the invention will be explained in conjunction with the accompanying drawings.

[0045]FIG. 7 is a diagram illustrating a DLL circuit according to a first preferred embodiment of the invention.

[0046]With reference to FIG. 7, the DLL circuit 100 according to this preferred embodiment comprises: phase shifting means 120 which, based on an input signal 300, generates, for example, 8 phase shifting processing signals 310 having phase differences at equal spacings (45 degrees); phase comparison means 140 which compares the phase of the input signal 300 with the phase of an output feedback signal 330 to detect a phase difference and, based on the detected phase difference, outputs a phase control signal 340; phase synthesizing means 160 which outputs a phase corrected signal 320 having a predetermined phase relationship with the input signals 300 based on the 8 phase shifting processing signals 310, generated by the phase shifting means 120, and the phase contr...

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PUM

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Abstract

A DLL (delay locked loop) circuit for outputting a phase lock signal having a predetermined phase relationship with an input signal. The DLL circuit has: a functional block having a constant-current source; and bias generator for generating a constant current source bias signal for controlling the constant current source of the functional block, the bias generator comprising a bias control which changes the bias signal according to the frequency of the input signal.

Description

FIELD OF THE INVENTION[0001]The invention relates to a DLL (delay locked loop) circuit which outputs a phase lock signal having a predetermined phase relationship with an input signal, and more particularly to a DLL circuit which, when the frequency of the input signal has been brought to a low frequency, can efficiently reduce power consumption while stably maintaining the operation.BACKGROUND OF THE INVENTION[0002]FIG. 1 is a block diagram showing the construction of a DLL circuit disclosed in Japanese Patent Laid-Open No. 17179 / 1997 (hereinafter referred to as “first conventional technique”).[0003]The DLL circuit according to the first conventional technique comprises; a four-phase basic clock generation circuit 541 which generates four phase clocks different from one another in phase by 90 degrees relative to an input clock 601 having a frequency f; a phase detection circuit 542 for detecting a phase relationship between the input clock 601 and an output clock 603; a phase regul...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H03D3/24G11C11/407G06F1/12H03K5/04H03L7/00H03L7/08H03L7/081
CPCH03L7/0802H03L7/0814H03L7/0816H03L7/00
Inventor MIYANO, KAZUTAKA
Owner LONGITUDE SEMICON S A R L
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