3 results about "Half cycle" patented technology

The invention relates to the electronic field, and discloses dimming method and circuit and a controllable silicon dimming circuit with the circuit. The method comprises the steps that a dimming signal is generated according to a current direct current input voltage signal; according to the dimming signal, the voltage average value signal of the dimming signal is generated; the fact that the dimming signal is currently in a positive half cycle or a negative half cycle is determined; when the dimming signal is currently in the positive half cycle, the voltage average value signal is compared with an output current feedback signal which represents the magnitude of the current output current, and a first comparison signal is output; a drive signal is output according to the first comparison signal; when the dimming signal is currently in the negative half cycle, the voltage average value signal is compared with an output current feedback signal which represents the magnitude of the current output current, and a second comparison signal is output; and a drive signal is output according to the second comparison signal. The application of the technical scheme is conductive to eliminating stroboflash.

A totem-pole power factor correction circuit (totem-pole PFC) is connected behind an input inductor receiving electric power from an alternating current (AC) power source. The totem-pole PFC is provided, in a high-frequency working area thereof, with at least two current transformer elements or a center-tapped current transformer element. The waveform of current flowing through the totem-pole PFC during positive and negative half cycles of AC power is sensed via the current transformer elements or the center-tapped current transformer element. Thereby, current waveform for the input inductor during positive and negative half cycles may be realized via the obtained current waveform completely, such that the practical problems originating from the conventional necessity for the establishment of bulky Hall device or another current-sensing unit are solved specifically.

A synchronous clock signal can be adjusted relative to a data signal by decreasing a delay in the synchronous clock signal if a transition of a data signal occurs before a pulse of an offset clock signal which is delayed by one half cycle relative to the synchronous clock signal. The synchronous clock signal can be delayed if the transition of the data signal occurs after the pulse of the offset synchronous clock signal.