E-mode hfet device

A FIG. 4

[0077]FIG. 4 is showing a Hetero-structure FET (HFET) device according to the preferred embodiment of the invention. The metallic or n+-type semiconductor regions 28 and 25 define the source and the drain of the transistor. Regions 29 corresponds to the barrier layer of the device, and the channel layer 27 is the region where the electron (or hole)—channel is formed. Region 23, which is formed by a heavily doped semiconductor layer on the top of an insulating layer 24, corresponds to the gate of the device.

[0078]If the desired device is an n-channel HFET, the channel region should have an electron affinity greater with respect to the barrier layer 29, in order to confine the carrier transport inside the layer 27 during the normal operation of the device. The gate region 23 instead, can be built with the same, greater or lower electron affinity with respect to the barrier layers, depending on the desired device characteristics. If necessary, the gate 23 and / or the barrier laye