Preparation method of 3D peripheral grid MOS tube

The invention provides a method for preparing a 3D surrounding gate MOS transistor, comprising the steps of: forming an N-type well and a P-type well isolated by a shallow trench isolation structure on a silicon substrate; Silicon nanowires are grown on the region to form NPN nanowires and PNP nanowires respectively; after continuing to deposit an oxide isolation layer and planarize, remove the oxide isolation layer located in the middle; sequentially deposit the gate oxide layer and polysilicon , and after etching away the polysilicon located between the NPN nanowire and the PNP nanowire, deposit an oxide isolation layer; remove part of the oxide isolation layer to expose part of the polysilicon covering the NPN nanowire and the PNP nanowire, and The exposed polysilicon is removed; after the oxide isolation layer is deposited again, the source, drain and gate are prepared to form a MOS transistor. The method is easy to operate, improves the control ability of the gate to the channel and improves the performance of the device.