An
image processing circuit, such as a
graphics accelerator
chip or any other suitable circuit, includes display output
control logic that is operative to receive a current frame of information from a frame buffer and is operative to process a current frame, such as by providing
gamma correction, image scaling,
graphics or video overlaying, or other suitable
processing, to produce a processed current display frame and stores the processed current display frame back in the frame buffer.
Fixed function or dedicated, display
type specific temporal
processing logic receives the processed current display frame stored in the frame buffer and also obtains at least one previous processed current display frame from the frame buffer and temporally processes pixels from each of the processed current display frame and the previous processed current display frame to produce a temporally compensated display frame for a specific type of display.