1 results about "Physical verification" patented technology

The invention discloses a clock tree layout flow method in an integrated circuit, in particular comprising the following steps: step 1, a top layer layout; 2, physical realization of a hard module; 3,extracting the clock tree information in the hard module; 4, acquire that clock tree deviation between the hard modules; 5, insert a clock tree deviation compensating device into that top-level module T; 6, generate a top-level clock tree in that top-level module T; 7, wire generation is carried out on that signal interconnection between each hard module in the top-layer module T; 8, extracting the interface timing model of the hard module when the static timing analysis of the whole chip is carried out; 9, static timing analysis of the whole chip; Step 10: physical authentication. The invention can reduce the level of the clock tree and the difficulty of balancing the clock tree. At the same time, a clock tree deviation compensation device is proposed for this flow method, which can effectively reduce the difficulty of timing convergence between hard modules.