Instruction execution method for vector complex multiplication operation and corresponding device

A technology of complex number multiplication and instruction execution, applied in the field of microprocessor architecture, can solve the problems of long pipeline series, instruction window control queue blockage, increase of processor area, etc., to save area and cost, avoid expansion, and avoid complexity degree of effect

Active Publication Date: 2010-09-08
LOONGSON TECH CORP
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Problems solved by technology

The disadvantages of this implementation method are: 1. The number of pipeline stages is long, and the pipeline start-up time is long, which easily leads to insufficient instruction windows and blockage of each control queue; 2. Multiplication and addition are separate arithmetic units, which increases the area of ​​the processor. , which

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[0023] As mentioned above, the present invention aims to reduce the pipeline length and hardware implementation cost of vector complex number multiplication, and the main idea of ​​its invention is to use two instruction pairings to complete vector complex number multiplication operations. Among them, the first instruction is a vector complex number. For the multiplication operation, the second instruction performs vector complex multiplication and addition operations. In addition, the two instructions multiplex the vector multiply-add functional unit, and two floating-point single-precision and one floating-point double-precision multiplex a vector multiply-add functional unit.

[0024] reference Picture 9 The block diagram of the vector multiply-add function unit of the present invention is shown. Taking the operand as 256 bits as an example, the operation of the vector multiply-add function unit is explained in detail as follows: a vector multiply or vector multiply-add instruct

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Abstract

The invention relates to an instruction execution method for vector complex multiplication operation (a+bj)*(c+dj) in a processor and a corresponding device. The method is characterized by comprising the step of designing two instruction matching pairs to finish the vector complex multiplication operation (a+bj)*(c+dj), wherein the first instruction executes vector multiplication, and the operation numbers of the first instruction comprise (a+bj) and (c+dj) for calculating partial results of the vector complex multiplication operation (a+bj)*(c+dj); and the second instruction executes vector multiplication and addition, and the operation numbers of the second instruction comprise the (a+bj), the (c+dj) and execution results of the first instruction for calculating rest results of the vector complex multiplication operation (a+bj)*(c+dj) and adding the rest results and the partial results to obtain a final result of the vector complex multiplication operation (a+bj)*(c+dj). By designing the two instruction matching pairs to finish the operation, the flow length of the vector complex multiplication operation is a flow grade of the multiplication and addition operation. Moreover, the method can greatly save the area and cost of a chip by complexing vector multiplication and addition functional components of the two instructions.

Description

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Claims

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Application Information

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Owner LOONGSON TECH CORP
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