Vertical field effect transistor formation with critical dimension control

[0037]As mentioned above, as mentioned above critical dimension control (e.g., control of gate length, control of alignment of top and bottom junction doping to gate edges, etc.) can be challenging with current methods of forming vertical field effect transistors (VFETs). For example, the lengths of the lower and upper spacers, which define the spacing between the channel region and the lower and upper source / drain regions, respectively, of a VFET are achieved by depositing spacer material and then recessing the spacer material using a timed etch process. Similarly, the length of the gate of a VFET is defined by depositing sacrificial gate material and then recessing the sacrificial gate material using a timed etch process. However, those skilled in the art will recognize that there can be a lot of process variation when using timed etch processes. As a result, VFET performance variations (e.g., variations in threshold voltage) can occur.

[0038]In view of the foregoing, disclosed here