Display device and electronic device
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Example
Embodiment 1
[0092]In this embodiment, a structure of a display device of one embodiment of the present invention will be described.
[0093]FIG. 1 is a block diagram showing a configuration example of a display device 1000. The display device 1000 includes a display unit 100, a touch sensor unit 200, a sensor 441, and a host device 440. In particular, the details of a controller IC (integrated circuit) 400 included in the display unit 100 are shown. The display unit 100 is a display unit including one of a liquid crystal element, a light-emitting element, and the like as a display element.
[0094]The display unit 100 includes a display portion 102, a gate driver 103, a level shifter 104, and a source driver IC 111 in addition to the controller IC 400. Note that the display element is included in the display portion 102.
[0095]The controller IC 400 includes an interface 450, a frame memory 451, a decoder 452, a sensor controller 453, a controller 454, a clock generation circuit 455, an image
Example
Embodiment 2
[0186]In this embodiment, a method for correcting an image using the host device 440, the sensor 441, and the image processing portion 460 in the controller IC 400 or 400A described in Embodiment 1 will be described. Note that for the method for correcting an image, a neural network is used.
[0187]A neural network is an information processing system modeled on a biological neural network. A computer having a higher performance than a conventional Neumann computer is expected to be provided by utilizing the neural network, and in these years, a variety of researches on a neural network formed over an electronic circuit have been carried out.
[0188]In the neural network, units which resemble neurons are connected to each other through units which resemble synapses. By changing the connection strength, a variety of input patterns are learned, and pattern recognition, associative storage, or the like can be performed at high speed.
[0189]For example, a product-sum operation circui
Example
Example 1 of Circuit for Constructing Hierarchical Neural Network
[0211]Next, a configuration example of a product-sum operation circuit for constructing the above-described hierarchical neural network will be described.
[0212]FIG. 11 is a block diagram of the semiconductor device 700 that serves as a product-sum operation circuit. The semiconductor device 700 includes an offset circuit 710 and a memory cell array 720.
[0213]The offset circuit 710 includes column output circuits OUT[1] to OUT[n] (here, n is an integer greater than or equal to 1) and a reference column output circuit Cref.
[0214]In the memory cell array 720, m (here, m is an integer greater than or equal to 1) memory cells AM are arranged in the column direction and n memory cells AM are arranged in the row direction; that is, m×n memory cells AM are provided. The total number of the memory cells AM and the memory cells AMref arranged in a matrix in the memory cell array 720 is m×(n+1). In particular, in the memory cell arr
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