5 results about "Digital input" patented technology

The invention discloses an automatic test system and method for communication control devices. The system comprises a main control module, a communication module, an acquisition module, a power sourcemodule and a human-machine interface; the main control module simulates a control unit to electrify a control device, and thereafter, sends a power source back-test command, a communication detectioncommand, a DO (digital output) command, a DI (digital input) command, an AD acquisition command, a control command, a function test command and a position data command; power source back-test information, communication response data, DO detection data, DI data, AD acquisition data, control response data, functional test response data and GNSS position information are analyzed according to a preset communication protocol and are compared with main control module standard values; test results are fed back to the human-machine interface; and therefore, problems brought about by a condition thatan existing control system only has a single function and single interface can be solved, and the functions of a plurality of communication control devices can be tested. Since the main control module, the communication module, the acquisition module, the power source module, a switching quantity input and output module and the human-machine interface are integrated, the communication control devices can be automatically tested, and test efficiency is significantly improved.

A fractional rate converting filter in a wireless transceiver comprising a delay line, multiplier circuit, adder circuit, and selector. The delay line receives a digital input signal at a first sample rate and has delay blocks each providing an output and receiving samples gated at a plurality of clock cycles of an integer sub-multiple frequency of a clock. The outputs are multiplied by corresponding filter tap coefficients. Each filter tap coefficient is spaced by a first integer Y. The adder circuit receives and sums the tap outputs to provide an output signal. The selector iteratively shifts the coefficients by a second integer Z. The output of each delay block is multiplied by corresponding shifted filter tap coefficients. The delay blocks are inhibited from receiving another input sample during the plurality of clock cycles. The output signal has a second sample rate at the integer sub-multiple frequency of the clock.