Junction field-effect transistor (JFET) pipe compatible process with double pole and P-ditch aligning automatically

The invention relates to a junction field-effect transistor (JFET) pipe compatible process with a double pole and a P-ditch aligning automatically. By means of grid region pre-oxidation, ditch region boron filling, grid region phosphorus filling and the annealing process, a method for manufacturing a double pole and grid self-aligning P-ditch JEFT compatible integrated amplifier is achieved. By means of the JEFT pipe compatible process, the shortcomings that a grid source/leakage overlapping parasitic capacitance formed by the existing non-self-aligning grid is large, a source end resistor and the drift region length are both large, and the device depends on graph dimension and dosage concentration of the ditch region and the drift region are overcome. The P-ditch JFET pipe process with the grid aligning automatically has the advantages of achieving self aligning of the grid region and the source/leak region, and reducing the drift region length of the grid source/leak overlapping parasitic capacitance and the source end resistance and the leakage end; and the P-ditch JEFT pipe is large in output dynamic resistance and, good in consistency of transconductance and punch-off voltage, and small in detuning and leakage current.