Arithmetic device for obtaining modular multiplication results of homologous passwords

A computing device and cryptographic technology, applied in the field of cryptography, can solve problems such as high delay and slow computing speed of computing devices, and achieve the effects of increasing computing speed, reducing computing delay, and solving high delay

Pending Publication Date: 2021-04-20
NANJING UNIV
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Problems solved by technology

[0004] This application provides a computing device for obtaining the result of modular multiplication of homol

Method used

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Example Embodiment

[0047] The embodiments will be described in detail hereinafter, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following examples do not represent all implementations consistent with this application. These are merely examples of systems and methods consistent with aspects of the present application as recited in the claims.

[0048] like figure 1 As shown, an arithmetic device for obtaining the modular multiplication result of the homologous cipher, including a data acquisition unit, a data processing unit, a multiplication and addition unit, a simple element reduction and a post-processing unit:

[0049] The data acquisition unit is configured to acquire the finite number field F a and F b , the finite number field F a and F b is obtained by proces

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Abstract

The invention discloses an arithmetic device for obtaining modular multiplication results of homologous passwords. The device comprises a data acquisition unit, a data processing unit, a multiply-add unit, a reduction unit and a post-processing unit. The data acquisition unit is configured to acquire finite number fields Fa and Fb to be processed, the multiply-add unit is configured to perform multiply-add calculation on the finite number fields Fa and Fb to obtain a multiply-add calculation result Fc, the reduction unit is configured to execute reduction calculation on the multiply-add calculation result Fc to obtain a reduction result, and the post-processing unit is configured to execute post-processing operation on the reduction result to obtain a modular multiplication result. Through parallel calculation of a reduction result, the operation speed is increased, the operation delay is reduced, and the problems of high delay and too low operation speed of an existing operation device are solved.

Description

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Claims

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Application Information

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Owner NANJING UNIV
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