Chip sorting anti-dislocation method and device, terminal and storage medium

An anti-dislocation, chip technology, applied in image analysis, image data processing, instruments, etc., can solve the problem of easy dislocation in the chip sorting process, and achieve the effects of high accuracy, improved processing speed, and improved labor efficiency.

Pending Publication Date: 2022-04-15
河北博威集成电路有限公司
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present invention provides a chip sorting anti-displacement method, device, terminal and

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0053] In the following description, specific details such as specific system structures and techniques are proposed for explanation, such as specific details such as specific system structures, and techniques. However, those skilled in the art will appreciate that the present invention can also be implemented in other embodiments without these specific details. In other cases, detailed description of well known systems, devices, and methods is omitted to prevent unnecessary details to prevent the description of the present invention.

[0054]In order to make the objects, technical solutions, and advantages of the present invention, the following will be described with reference to the accompanying drawings.

[0055] Next, an embodiment of the present invention will be described in detail, and the present example is implemented in the preparation of the present invention, the detailed embodiment and the specific operation process are given, but the scope of the invention is not limit

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to the technical field of semiconductor device manufacturing, in particular to a chip sorting dislocation prevention method and device, a terminal and a storage medium, and the method comprises the steps: obtaining a wafer image, carrying out the preprocessing of the wafer image, obtaining the coordinates of a taken chip and the coordinates of a non-taken chip through the preprocessed wafer image, and obtaining the coordinates of the taken chip and the coordinates of the non-taken chip; the coordinate is compared with the MAP to determine whether the taken-down chip is consistent with the indication of the MAP, so that the problem of mistaken taking caused by accumulated error of the chip position of the wafer taken out by the equipment when the row and column spacing of the wafer is inconsistent in the sorting stretching frame can be avoided. According to the method, the chip taking accuracy is high, when the method is operated on a computing terminal, the processing speed can be greatly increased, the manual confirmation and tracking process is reduced, and the labor efficiency is improved.

Description

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Owner 河北博威集成电路有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products