Verification method for connection sequence of signal line and power line

A verification method and signal line technology, applied in electrical digital data processing, instruments, calculations, etc., can solve the problems of easy missed detection and low efficiency, and achieve the effect of improving accuracy and efficiency

Pending Publication Date: 2022-07-29
四川创安微电子有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present technology allows for accurate identification between two signals (the one being connected) by automatically checking if they are correctly connected together before supplying electricity or receiving data from them. This helps improve the overall performance and reliability of these circuits during their use.

Problems solved by technology

The technical problem addressed in this patented text relates to improving efficiency during circuit designs validation for larger scale integration (LSI) chips without requiring manual observation or subjective judgment on their connection between different lines.

Method used

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  • Verification method for connection sequence of signal line and power line
  • Verification method for connection sequence of signal line and power line
  • Verification method for connection sequence of signal line and power line

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Embodiment Construction

[0032] In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and the accompanying drawings. as a limitation of the present invention.

[0033] The improvement of the present invention over the prior art lies in that, in the design of a large-scale integrated circuit, an automatic check is realized for the verification that the signal line is connected before the power line.

[0034] An embodiment of the present invention provides a method for verifying the connection sequence of a signal line and a power line, including the following steps:

[0035] S1. Export the IC layout to DEF files and GDS files;

[0036] The DEF file is a text file that records layout information, including the coordinates and names of modules, lines, etc.;

[0037] GDS file is a graphic file that records layout information, including coordinates and names of modul

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Abstract

The invention discloses a method for verifying the connection sequence of a signal line and a power line. The method comprises the following steps: exporting an integrated circuit layout to a DEF file and a GDS file; extracting effective information to a database X by utilizing the DEF file; automatic verification is carried out, and an error result is output; and correcting the error result, and returning to the above steps until no error result is output. According to the method, the connection sequence of the signal line and the power line of the large-scale integrated circuit can be verified, and the verification accuracy and efficiency are effectively improved.

Description

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Claims

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Application Information

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Owner 四川创安微电子有限公司
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