Apparatus and method for direct memory access in a hub-based memory system

a memory system and hub-based technology, applied in the field of computer systems, can solve the problems of slow memory controllers and memory devices, limiting the data bandwidth between the processor and the memory device, and increasing the operating speed of processors,

Inactive Publication Date: 2005-01-27
ROUND ROCK RES LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the operating speed of memory devices has continuously increased, this increase in operating speed has not kept pace with increases in the operating speed of processors.
The relatively slow speed of memory controllers and memory devices limits the data bandwidth between the processor and the memory devices.
In addition to the limited bandwidth between processors and memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from system memory devices.
Therefore, although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices.
Although computer systems using memory hubs may provide superior performance, they nevertheless may often fail to operate at optimum speeds for a variety of reasons.
For example, even though memory hubs can provide computer systems with a greater memory bandwidth, they still suffer from latency problems of the type described above.
More specifically, although the processor may communicate with one memory device while another memory device is preparing to transfer data, it is sometimes necessary to receive data from one memory device before the data from another memory device can be used.
In the event data must be received from one memory device before data received from another memory device can be used, the intervention of the processor continues to slow the operating speed of such computer systems.
Another one of the reasons such computer systems fail to operate at optimum speed is that conventional memory hubs are essentially single channel systems since all control, address and data signals must pass through common memory hub circuitry.
As a result, when the memory hub circuitry is busy communicating with one memory device, it is not free to communicate with another memory device.
As a result, the value of having DMA operations is diminished to some degree because the processor ultimately becomes involved by moving data around in memory despite the use of a DMA operation in the data transfer to and from the system memory.

Method used

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Embodiment Construction

[0017] Embodiments of the present invention are directed to a system memory having a memory hub architecture including direct memory access (DMA) capability to transfer data within the system memory without the intervention of a system processor. Certain details are set forth below to provide a sufficient understanding of the invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. In other instances, well-known circuits, control signals, and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention.

[0018] A computer system 100 according to one example of the invention is shown in FIG. 1. The computer system 100 includes a processor 104 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 104 includes a processor bus 106 that normally includes an address bus, a control bus, and a ...

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PUM

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Abstract

A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations.

Description

TECHNICAL FIELD [0001] This invention relates to computer systems, and, more particularly, to a computer system including a system memory having a memory hub architecture. BACKGROUND OF THE INVENTION [0002] Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data that are accessed by a processor. These memory devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data are transferred between the system memory a...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06FG06F13/28G06F13/40
CPCG06F13/4009G06F13/28G06F13/20G06F13/16
Inventor JEDDELOH, JOSEPH M.
Owner ROUND ROCK RES LLC
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