Error notification method and information processing apparatus

a technology of information processing apparatus and error notification method, which is applied in the field of error notification method and information processing apparatus, can solve the problems of computer system shutdown, software cannot be modified, and the error process handler of each cpu within the computer system normally cannot be modified, so as to reduce the error level of a corresponding error interrupt signal

Inactive Publication Date: 2006-09-21
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The technical effect of this patented technology relates to improving fault notifications during data transmission between two processors operating at different modes or even simultaneously without affecting their performance. This can be useful particularly where there are multiple sources of errors such as hardware failures or software bugs.

Problems solved by technology

This patent describes different ways to improve upon error notifications sent over communication networks between computers without affecting their performance. One way involves sending them separately but coordinating multiple modules based on certain criteria. Another approach uses hardware devices called Error Display Register Units (ELDUs), which store data indicating how many times they have been wrong during execution. If these incorrect actions occur while receiving messages containing important details about what happened at once, then the message can be stopped until after correction succeeds. Additionally, some techniques involve modifying programs themselves to prevent crashes caused by malfunctions.

Method used

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  • Error notification method and information processing apparatus
  • Error notification method and information processing apparatus
  • Error notification method and information processing apparatus

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Embodiment Construction

[0023] A description will be given of embodiments of an error notification method and an information processing apparatus according to the present invention, by referring to FIG. 2 and the subsequent drawings.

[0024]FIG. 2 is a system block diagram showing a general structure of the information processing apparatus according to the present invention. An embodiment of the information processing apparatus according to the present invention employs an embodiment of the error notification method according to the present invention. In this embodiment, the present invention is applied to a computer system shown in FIG. 2.

[0025] A computer system 10 shown in FIG. 2 includes a system board 11 that is used in a normal mode, a system board 12 that is used together with the system board 11 in a mirror mode, an input and output (I / O) board 142 having a plurality of input and output (I / O) ports, and a home system board 13 that processes errors detected in the system boards 11 and 12. In other

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Abstract

An error notification method notifies errors generated in first and second processor systems to each processor within the first and second processor systems, in a computer system that includes the first processor system operable in a normal mode and the second processor system operable together with the first processor system in a mirror mode. The error notification method generates an error interrupt signal that indicates each error by a corresponding one of a plurality of error levels, reduces the error level of a corresponding error interrupt signal when the error within the first processor system is avoided in the mirror mode, and notifies the error to each processor within the first and second processor systems using the error interrupt signal.

Description

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Claims

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Application Information

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Owner FUJITSU LTD
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