Nonvolatile memory device, system comprising nonvolatile memory device, and read operation of nonvolatile memory device

[0036]Embodiments of the inventive concept are described below with reference to the corresponding drawings. These embodiments are presented as teaching examples and should not be construed to limit the scope of the inventive concept.

[0037]FIG. 1 is a block diagram of a nonvolatile memory device according to an embodiment of the inventive concept.

[0038]Referring to FIG. 1, a nonvolatile memory device 100 comprises a memory cell array 110, a high voltage generator 120, a row decoder 130, a page buffer 140, a Y-gate 150, and a control circuit 160.

[0039]Memory cell array 110 comprises a plurality of multi-level cells each configured to store multiple bits of data. The multi-level cells are connected to corresponding wordlines and bitlines.

[0040]High voltage generator 120 generates wordline voltages Vvrf, Vrd, and Vpgm to be supplied to memory cell array 110. High voltage generator 120 generates different wordline voltages according to different operational modes, such as a read operation