2 results about "Internal logic" patented technology

The invention discloses a verification method for a chip reset test scene. The verification method comprises the following steps: creating a process processor, a reset subscriber and a reset notifier; an apply method is provided for a process processor; the reset subscriber comprises a base class thereof; and a subscript method and a notify method are provided for a reset notifier. Compared with the prior art, the method has the following beneficial effects: (1) the verification test framework in the reset scene provided by the invention can realize that a verification environment can stop initiating an excitation request when monitoring that a reset signal is valid, and some internal logic states of all related components can be correspondingly cleared; (2) according to the verification test framework in the reset scene, after the reset signal is released, the verification environment can restart to apply and initiate the excitation request, and all the components can normally run again.