Verification method for chip reset test scene

A technology for testing scenarios and verification methods, which is applied in the fields of instruments, computing, electrical and digital data processing, etc., and can solve the problems of easy-to-miss reset scenario testing, increased difficulty in code management and maintenance, and difficulty in debugging when problems occur.

Pending Publication Date: 2022-08-09
杭州云合智网技术有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] (1) In the encapsulation environment corresponding to each sub-module, the processing action logic style for the reset scenario is different, which increases the difficulty of later code management and maintenance
[0012] (2) Since there is no uniform standard framework to follow, it is easy to miss the test of some detailed characteristics in the reset scenario. For example, after the reset signal is valid, whether the target test stimulus is re-initiated or continues to be initiated following the original stimulus. At this time, the verification What processing actions should the components take?
[0013] (3) When the packaging environment corresponding to these sub-modules is integrated and verified to a higher level, it will be difficult to debug when problems occur

Method used

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  • Verification method for chip reset test scene
  • Verification method for chip reset test scene
  • Verification method for chip reset test scene

Examples

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Embodiment Construction

[0056] The following will be combined with the attachment to describe the preferred embodiments of the present invention in detail to further explain the present invention.

[0057] First, it will be combined Figure 2 ~ 3 The 5 ~ 6 description is based on the verification method of the chip reset testing scenario based on the examples of the present invention. It is used for chip verification and use, and its application scenarios are wide.

[0058] like image 3 It shows that the verification method of the embodiment of the present invention has the following steps:

[0059] In S1, such as image 3 Show, the processing processor process_handler, resetner Reset_Subscriber, and resetter Reset_blogger. Provide the Apply method to the processing processor to operate the current simulation operation according to the type of reset notification message. The reset notification information type Reset_blogger_notification_t is an enumeration variable that operates the process process, includ...

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Abstract

The invention discloses a verification method for a chip reset test scene. The verification method comprises the following steps: creating a process processor, a reset subscriber and a reset notifier; an apply method is provided for a process processor; the reset subscriber comprises a base class thereof; and a subscript method and a notify method are provided for a reset notifier. Compared with the prior art, the method has the following beneficial effects: (1) the verification test framework in the reset scene provided by the invention can realize that a verification environment can stop initiating an excitation request when monitoring that a reset signal is valid, and some internal logic states of all related components can be correspondingly cleared; (2) according to the verification test framework in the reset scene, after the reset signal is released, the verification environment can restart to apply and initiate the excitation request, and all the components can normally run again.

Description

Technical field [0001] The invention involves the field of chip detection technology, which specializes in a verification method in the chip reset testing scenario. Background technique [0002] When we verify the RTL design (also known as DUT, test device), we often need to verify the reset scene, that is, during the normal operation of DUT, the reset signal is set to an effective state to reset the DUT. After a delay of a clock cycle, the reset signal is released to restart DUT. [0003] like figure 1 Show, you can see, figure 1 The mid -clock signal CLK has been flipping normally, and the low level effective reset signal RST_N is low at the beginning of the simulation operation. At this time, DUT enters the normal working state. At this time, we can apply for testing incentives REQ1 ~ N to test the duT function, but the reset signal is placed again in the process of simulation operation to reset the DUT. At this time, at this time Test incentives no longer continue to send the...

Claims

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Application Information

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IPC IPC(8): G06F30/3308
CPCG06F30/3308
Inventor 马骁
Owner 杭州云合智网技术有限公司
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