High speed parallel concatenated code coder decoder

A decoder and concatenated code technology, applied in the application of multi-bit parity error detection coding, error correction/detection using block codes, digital transmission systems, etc., to achieve improved equipment mobility, simplified structure, light weight effect

Active Publication Date: 2012-05-23
NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented technical effect lies within this patents that includes various improvements over existing technologies for coding and transmission of digital signals like video or audio streams through communication networks. These advancements include faster speeds, more efficient use of bandwidth resources, better error detection capabilities, easier implementation across multiple platforms, higher reliance levels (long lasting) without requiring expensive repairs after installation, smaller sizes, lighter weights, longer lifespan), enhanced functionality beyond just sending compressed analogue signal samples via wireless connections, increased efficiency when compared to older methods, and greater ease of handling during operation.

Problems solved by technology

The technical problem addressed by this patented technology relates to improving the efficiency at which traditional methods can compress or decode large amounts of data quickly without requiring more resources than necessary. This limitation makes it hard to achieve higher speeds when transmitting these types of signals over communication networks like wireless LANs (WLAN).

Method used

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  • High speed parallel concatenated code coder decoder
  • High speed parallel concatenated code coder decoder
  • High speed parallel concatenated code coder decoder

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Embodiment Construction

[0022] refer to Figure 1 to Figure 3 , the encoder of the present invention includes a shunt converter 1, RS encoder groups 2-1, 2-2, 2-3, 2-4, frame inserter groups 3-1, 3-2, 3-3, 3 -4, interleaver group 4-1, 4-2, 4-3, 4-4, convolution code encoder group 5-1, 5-2, 5-3, 5-4; phase is included in the decoder Converter 6, convolutional code decoder group 7-1, 7-2, 7-3, 7-4, frame searcher group 8-1, 8-2, 8-3, 8-4, deinterleaver Groups 9-1, 9-2, 9-3, 9-4, RS decoder groups 10-1, 10-2, 10-3, 10-4; composed. figure 1 It is a block diagram of the implementation principle of the high-speed parallel concatenated code encoder embodiment of the present invention, figure 2 It is a block diagram of the realization principle of the high-speed parallel concatenated code decoder embodiment of the present invention, and the embodiment is according to figure 1 , figure 2 connect.

[0023]In the high-speed parallel concatenated code encoder, pin 1 of the input terminal of the shunt convert

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Abstract

The invention discloses a high speed parallel concatenated code coder decoder, which is widely applied to satellite communication systems, deep space communication systems and the like. The high speed parallel concatenated code coder decoder comprises a coder and a decoder, wherein the coder comprises a branch convertor, a first remote sensing (RS) coder, a second RS coder, a third RS coder, a fourth RS coder, a first frame inserting device, a second frame inserting device, a third frame inserting device, a fourth frame inserting device, a first interleaver group, a second interleaver group, a third interleaver group, a fourth interleaver group, a first convolutional code coder, a second convolutional code coder, a third convolutional code coder and a fourth convolutional code coder; and the decoder comprises a phase convertor, a first convolutional code decoder, a second convolutional code decoder, a third convolutional code decoder, a fourth convolutional code decoder, a first frame searching device, a second frame searching device, a third frame searching device, a fourth frame searching device, a first deinterleaver, a second deinterleaver, a third deinterleaver, a fourth deinterleaver, a first RS decoder, a second RS decoder, a third RS decoder and a fourth RS decoder. The coder directly performs concatenated code coding on high speed serial data through a high speed parallel technology, and transmits the coded data to modulation equipment in a parallel mode; and the decoder directly performs concatenated code decoding on parallel data with phase ambiguity output by a demodulator, and problems of sequence randomness of the parallel data, random malalignment of the parallel data and the like caused by the randomness of analog/digital (AD) sampling time can be solved.

Description

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Claims

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Application Information

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Owner NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP
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