High speed parallel concatenated code coder decoder
A decoder and concatenated code technology, applied in the application of multi-bit parity error detection coding, error correction/detection using block codes, digital transmission systems, etc., to achieve improved equipment mobility, simplified structure, light weight effect
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[0022] refer to Figure 1 to Figure 3 , the encoder of the present invention includes a shunt converter 1, RS encoder groups 2-1, 2-2, 2-3, 2-4, frame inserter groups 3-1, 3-2, 3-3, 3 -4, interleaver group 4-1, 4-2, 4-3, 4-4, convolution code encoder group 5-1, 5-2, 5-3, 5-4; phase is included in the decoder Converter 6, convolutional code decoder group 7-1, 7-2, 7-3, 7-4, frame searcher group 8-1, 8-2, 8-3, 8-4, deinterleaver Groups 9-1, 9-2, 9-3, 9-4, RS decoder groups 10-1, 10-2, 10-3, 10-4; composed. figure 1 It is a block diagram of the implementation principle of the high-speed parallel concatenated code encoder embodiment of the present invention, figure 2 It is a block diagram of the realization principle of the high-speed parallel concatenated code decoder embodiment of the present invention, and the embodiment is according to figure 1 , figure 2 connect.
[0023]In the high-speed parallel concatenated code encoder, pin 1 of the input terminal of the shunt convert
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