Selector circuit with fixed output state

The invention discloses a selector circuit with a fixed output state, relating to an integrated circuit technology. A selector comprises a transmission gate, a phase inerter and a PMOS (P-channel Metal Oxide Semiconductor) up-drawing tube. Control bits output by a control circuit are connected with the grid electrode of an NMOS (N-channel Metal Oxide Semiconductor) tube of the transmission gate and used for controlling the grid electrode of a PMOS tube of the transmission gate through the phase inverter, the grid electrode of the PMOS up-drawing tube is connected with the control bits, the source electrode of the PMOS up-drawing tube is connected with a power supply end vdd, and the drain electrode of the PMOS up-drawing tube is connected with the output end of the transmission gate. The circuit disclosed by the invention can be used for ensuring that the output end of the selector is not in an empty level state, but is drawn to the high level through the PMOS up-drawing tube when all output control bits are equal to zero, so that a static short-circuit current is prevented from being generated by a gate circuit connected with the output end; and the circuit disclosed by the invention is low in area overhead, low in requirement for parameters of the PMOS up-drawing tube, capable of reducing the amount of the control bits and eliminating the static short-circuit current, and little in influence to the performance of a chip.