Generating method for test chip layout
A layout and chip technology, applied in the field of test chip layout generation, can solve the problems of error-prone test structure, low area utilization rate, high test cost, etc., and achieve the goal of reducing process test cost, improving test accuracy, and improving area utilization rate Effect
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[0061] The present invention will be further described below in conjunction with the drawings and specific embodiments, but the protection scope of the present invention is not limited to this.
[0062] Such as figure 1 As shown, a method for generating the layout of a test chip is to first select the area of the chip to be tested, and then place it once or repeatedly to form a unit array, then connect the repeated units, and finally use the repeatedly connected unit as the test The structure is placed in the addressable test chip layout and wired. Specifically include the following steps:
[0063] (1) Generate test structure:
[0064] 1.1. Select a layout area that contains the required test location in the chip layout; image 3 In the middle, the left side is the chip layout, the middle is the selected layout area, and the right is the partial enlargement containing the required test location. Figure 4 In the middle, the left is the chip layout, and the middle is the selected lay
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