Semiconductor memory device, system with semiconductor memory device, and method for operating a semiconductor memory device

[0037]FIG. 1 shows a schematic representation of the structure of a semiconductor memory device 1 or semiconductor memory chip, respectively, and of a—central—memory device controller 5 according to an embodiment of the present invention.

[0038] The semiconductor memory device 1 may, for instance, be a table memory device based on CMOS technology, e.g. a RAM memory device (RAM Random Access Memory or read-write memory), in particular a SRAM memory device (SRAM=Static Random Access Memory) or a DRAM memory device (DRAM=Dynamic Random Access Memory or dynamic read-write memory) (e.g. a DDR-DRAM (DDR-DRAM=Double Data Rate DRAM).

[0039] In the semiconductor memory device 1, data may—after the input of a corresponding address—be stored under the respective address and be read out again under this address later.

[0040] The address may be input in several, e.g. two successive steps (e.g. first a row address (“row address”)—and possibly parts of a column address (“column address”)—, and then t