Semiconductor memory device

[0046]FIG. 1 shows a semiconductor memory device of the present invention. This semiconductor memory device is formed as a pseudo-SRAM on a silicon substrate using a CMOS process. The pseudo-SRAM is used, for example, for a work memory mounted in portable equipment such as a mobile phone.

[0047] The pseudo-SRAM includes input buffers 10, 12, 14, an output buffer 16, a command input circuit 18, a power control 20, a timing control 24 including an arbiter 22, delay circuits DLY1-3, a refresh timer (refresh request circuit) 26, a refresh address counter 28, a first address latch circuit 30, a multiplexer 32, second address latch circuits 34, 36, a row decoder 38, an input data latch circuit 40, an output data control 42, a configuration register 44, a column decoder 46, a sense amplifier / switch 48, a memory cell array 50, and plural specification setting units S1.

[0048] Each specification setting unit S1 is constituted of a conductive layer formed at a predetermined position on the sili

[0134] In the above second embodiment, the example in which the specification setting unit S1 is constituted of the fuse is described. The present invention is not limited to this embodiment. For example, the specification setting unit S1 may be constituted using an electrically programmable memory cell such as an EPROM, an EEPROM, or an FeRAM instead of the fuse.

[0135] Although the present invention is described in detail above, the above embodiments and their modified examples are merely illustrative of the invention, and the present invention is not limited to these. It is understood that various modifications may be made without departing from the scope of the present invention.

[0136] By applying the present invention to a semiconductor memory device which includes an address valid terminal and automatically performs refresh, a malfunction of the semiconductor memory device due to contention between a refresh operation and an access operation can be prevented.