Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality
a memory device and memory technology, applied in the direction of information storage, static storage, digital storage, etc., can solve the problems of reducing the signal quality of read data from the memory, and the problem of more pronounced problems
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[0065]Case #1 in FIG. 7 is one in which high-level data is written to a memory cell, where the transistor 301 is switched on, and the transistor 302 is switched off. The main I / O line MIO is thereby driven to a high level via the transistor 301. Case #2 is one in which low-level data is written to a memory cell, where the transistor 301 is switched off, and the transistor 302 is switched on. The main I / O line MIO is thereby driven to a low level via the transistor 302. Case #3 is one in which the main I / O line MIO is pre-charged, where the transistor 301 is switched on, and the transistor 302 is switched off. The main I / O line MIO is thereby pre-charged via the transistor 302. Case #4 is one in which a read operation is performed by a read circuit 200, where both the transistors 301 and 302 are switched off. The main I / O line MIO is thereby disconnected from the precharge circuit 300.
[0066]FIG. 8 is a circuit diagram of the assist circuit 400.
[0067]As shown in FIG. 8, the ass
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