Method to verify an implemented coherency algorithm of a multi processor environment

a multi-processor environment and verification method technology, applied in computing, memory adressing/allocation/relocation, instruments, etc., can solve problems such as not solving problems that are satisfying, and achieve the effect of reducing complexity and better control over stimuli

Inactive Publication Date: 2010-06-10
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a simplified method for validating coherence algorithms used by multiple processors in a simulated system. This reduces the number of steps needed and makes testing more efficient compared to traditional methods like comparing different versions of an algorithm or performing simulations. Additionally, this method ensures that each computer's behavior remains consistent even if there are changes made during execution.

Problems solved by technology

The technical problem addressed in this patent is how to verify if multiple processing units use older data without being able to access new data for longer periods of time while still maintaining their effectiveness. This requires testing coherence rules at different stages during the design phase of the system.

Method used

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  • Method to verify an implemented coherency algorithm of a multi processor environment
  • Method to verify an implemented coherency algorithm of a multi processor environment
  • Method to verify an implemented coherency algorithm of a multi processor environment

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Embodiment Construction

[0024]A multi processor environment consists of a communication fabric called nest that embeds several single processors. In order to get data each processor has to make fetch requests to the nest. The smallest data package that can be requested is a cacheline that contains several bytes of data. The same cacheline is allowed to be used in several processors, as long as it is marked as a read-only copy.

[0025]If a processor wants to change a byte in cacheline F it needs to get exclusive rights on that cacheline F. The processor sends an exclusive fetch request on cacheline F to the nest. The nest generates read-only cross invalidates for all other processors and informs the requesting processor that it is now allowed to change cacheline F. The other processors can use their old read-only copy of cacheline F as long as it is not observable to the outside world, that they have used old data. The usage of an old copy of cacheline F is not observable as long as that processor is only workin

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Abstract

A method to verify an implemented coherency algorithm of a multi processor environment on a single processor model is described, comprising the steps of:
    • generating a reference model reflecting a private cache hierarchy of a single processor within a multi processor environment,
    • stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side,
    • augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, set based on interface events,
    • wherein multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before.
Further a single processor model and a computer program product to execute said method are described.

Description

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Claims

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Application Information

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Owner IBM CORP
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