A
delay circuit has an input node receiveing an input pulsed
signal. A buffer transfers the input
signal to a floating node. A
detector outputs to an output node an output
voltage that has a first level, if the
voltage at the floating node is below a threshold, and a second level otherwise. Two similar branches are used, one for controlling delays in the rising transitions and one for controlling delays in the falling transitions. For each
branch, a reference terminal carries a reference
voltage for biasing the floating node. A
capacitor and a switch are coupled between the reference terminal and the floating node. The switch opens and closes responsive to the output voltage. When it opens, it shorts out the
capacitor. An optional
phase detector and
delay code generator may be in a feedback arrangement, for continuously adjusting the reference voltages.