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6 results about "Phase detector" patented technology

A phase detector or phase comparator is a frequency mixer, analog multiplier or logic circuit that generates a voltage signal which represents the difference in phase between two signal inputs. It is an essential element of the phase-locked loop (PLL).

A low phase noise broadband microwave frequency source circuit

ActiveCN109088634AReduce phase noiseAchieve the effect of low phase noisePulse automatic controlLoop filterPhase detector
The invention discloses a broadband microwave frequency source circuit with low phase noise. The reference frequency is input into a digital phase detector and a low phase noise amplifier respectively. The output end of the digital phase detector is connected with the input end of a passive loop filter, and the output end of the passive loop filter is connected with the first end of a plurality ofactive loop filters respectively. The output of the low phase noise amplifier is connected to the input of the sampling phase detector. The output of the sampling phase detector is connected to the input of the first set of multiplexers, the output terminals of the first group of multiplexers are respectively connected with the second terminals of a plurality of active loop filters, the third terminals of the plurality of active loop filters are respectively connected with the input terminals of the second group of multiplexers, the output terminals of the second group of multiplexers are respectively connected with a plurality of VCOs, and a plurality of VCOs select one output. The selected VCO output signal is fed back to the sampling phase detector as the system output and fed back tothe digital phase detector through the N divider. The invention realizes the effects of wide frequency band and low phase noise.
Owner:SOUTHEAST UNIV

Pulse Signal transforming delay regulating circuit

InactiveCN1388648AEliminate delaysEliminate coupling noiseSingle output arrangementsPulse shapingPhase detectorEngineering
A delay circuit has an input node receiveing an input pulsed signal. A buffer transfers the input signal to a floating node. A detector outputs to an output node an output voltage that has a first level, if the voltage at the floating node is below a threshold, and a second level otherwise. Two similar branches are used, one for controlling delays in the rising transitions and one for controlling delays in the falling transitions. For each branch, a reference terminal carries a reference voltage for biasing the floating node. A capacitor and a switch are coupled between the reference terminal and the floating node. The switch opens and closes responsive to the output voltage. When it opens, it shorts out the capacitor. An optional phase detector and delay code generator may be in a feedback arrangement, for continuously adjusting the reference voltages.
Owner:SAMSUNG ELECTRONICS CO LTD

Direction finding method and system based on radio frequency analog receiving system

ActiveCN111693936AAvoid the problem of unbalanced input signal amplitudeSolving Phase Blur ProblemsRadio wave finder detailsPhase detectorEngineering
The invention provides a direction finding method based on a radio frequency analog receiving system. The method comprises steps of obtaining the phase difference between each path of antenna and an adjacent antenna through a phase discriminator for an N-element uniform circular array antenna, and recording the phase difference as the phase difference of the phase discriminator; recording the phase difference of each phase discriminator as an initial phase difference when an incoming wave enters the circular array antenna at an elevation angle of 0 degree; constructing a plurality of phase discriminators corresponding to each phase discriminator; according to an elevation angle and an azimuth angle, k is the number of iterations, and calculating the theoretical phase difference of each phase discriminator; introducing a vector X and a direction vector G, and calculating an elevation angle and an azimuth angle of a two-dimensional incident angle of iteration times k+1 in combination with the constructed complex number, calculating the difference between the two-dimensional incident angle with the iteration frequency of k+1 and the iteration frequency of k, comparing the two-dimensional incident angle with a threshold value, and entering an output elevation angle and an azimuth angle when the two-dimensional incident angle is smaller than the threshold value, otherwise, adding 1to the value of k, and calculating the theoretical phase difference. The method is advantaged in that problems of logic judgment and other operations, phase ambiguity and unbalanced amplitude of an input signal of the phase discriminator are avoided, and direction finding precision is improved.
Owner:SOUTHWEST CHINA RES INST OF ELECTRONICS EQUIP

Phase locked loop with dual input reference and dynamic bandwidth control

PendingCN114640344APulse automatic controlSynchronising arrangementComputer hardwarePhase detector
Systems and methods for improved performance of phase-locked loop-based clock generators, particularly in the context of wireless audio, are disclosed herein. The PLL clock generator includes: a PLL core configured to receive a module reference clock provided by the communication module and generate a subsystem data clock corresponding to a module data clock of the communication module; and a data clock tracker module configured to receive the module data and the subsystem data clock and determine a corresponding data clock correction factor. In this way, the bandwidth of the PLL core can be dynamically changed, thereby achieving fast and very precise stabilization. The PLL core may use a low jitter frequency reference for the phase detector while using a synchronized and easily jitter audio sampling clock to ensure that the average frequency of the PLL core tracks the audio sampling clock.
Owner:SYNAPTICS INC
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