Phase locked loop with dual input reference and dynamic bandwidth control
一种锁相环、参考时钟信号的技术,应用在锁相环领域,能够解决失锁、增加系统复杂性和功耗、稳定时钟难以实现等问题
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[0022] The present disclosure provides systems and methods that address the need in the art for improved performance of phase locked loop (PLL) based clock generators used in low power devices. The PLL-based clock generator disclosed herein can maintain a relatively stable clock output by reference to the loss of the clock input and can consume less power than conventional systems while reducing or eliminating the clock errors associated with the clock errors present in conventional systems. Audio artifacts. In particular, embodiments can use a combination of reference and data clocks derived from communication modules to generate relatively stable and jitter-free system reference clocks and subsystem data clocks, even when the data clocks transition between frequencies or time bases. The reference clock can be used as the main PLL phase reference, while the data clock can be used to fine-tune the precise operating frequency to ensure that the received data rate (eg, audio sam...
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