5 results about "Clock generator" patented technology

A frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal, a frequency multiplier to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal, and a fractional-N synthesizer coupled to the frequency multiplier to generate an output clock signal in response to the frequency-multiplied clock signal.

Provided is a clock generator employed in a continuous-time sigma-delta modulator. The clock generator includes an oscillator configured to generate pulses in response to an enable signal, a counter configured to count the number of pulses generated by the oscillator and output the total pulse count, and an output circuit configured to output an inactivated output signal if the pulse count of the counter is equal to a pulse-width control bit. The oscillator includes an astable multi-vibrator. Since the astable multi-vibrator capable of generating a low-jitter pulse from a jittered clock is used as the oscillator, a signal-to-noise ratio is improved. A simple configuration using only digital circuits makes it easier to design a circuit and adjust pulse width. Moreover, according to the structure of the astable multi-vibrator, it is possible to design a circuit to optimally modulate pulse width in connection with process variations of resistors and capacitors used in the continuous-time sigma-delta modulator.

The invention provides a stable oscillation clock generated inside a chip, at least comprising an oscillation clock generator (OSC generator), a programming controller for controlling clocks with different frequencies and a timing counter, wherein a control signal output by the programming controller for controlling the clocks with the different frequencies is directly connected to the oscillation clock generator (OSC generator); an oscillation clock signal is generated by the oscillation clock generator; the oscillation clock signal is output to outside to be used by different parts of the chip; the oscillation clock signal is connected to the clock input end of the timing counter to adjust the counted quantity of the timing counter; and the counted quantity of the timing counter is connected to a comparator to be compared with a standard performance to generate a feedback signal to a logic control unit of the stable oscillation clock, so as to automatically determine the frequency of the oscillation clock. A designing method of the stable oscillation clock generated inside the chip enables the work of the chip to be more stable and reduces the error rate and the like; and the stable oscillation clock is compact in structure and is safe and reliable.