Systems and methods for
improved performance of phase-locked loop-based
clock generators, particularly in the context of
wireless audio, are disclosed herein. The PLL
clock generator includes: a PLL core configured to receive a module reference
clock provided by the communication module and generate a subsystem data clock corresponding to a module data clock of the communication module; and a data clock tracker module configured to receive the module data and the subsystem data clock and determine a corresponding data
clock correction factor. In this way, the bandwidth of the PLL core can be dynamically changed, thereby achieving fast and very precise stabilization. The PLL core may use a
low jitter frequency reference for the
phase detector while using a synchronized and easily
jitter audio sampling clock to ensure that the average frequency of the PLL core tracks the audio sampling clock.