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3 results about "Clock correction" patented technology

Method for determining service range of satellite-based augmentation system

PendingCN114152962AReasonable handlingImprove processing efficiencySatellite radio beaconingClock correctionIonosphere
The invention provides a method for determining a service range of a satellite-based augmentation system, which comprises the following steps of: selecting a target research area, resolving satellite augmentation orbit/clock correction and user difference ranging error information of a global navigation satellite system in a current epoch, calculating an orbit/clock correction comprehensive error of each satellite projected on a grid point in the current epoch, and determining the service range of the satellite-based augmentation system. Counting the UDRE envelope probability of grid points in a target area, calculating the delay error value of an ionosphere of the grid points and the vertical error information of the ionosphere of the grid, counting the GIVE envelope probability of the grid points in the target area, solving a union set for a public area under the integrity parameter envelope requirement, and determining a final SBAS service area. The union overlapped area is the final service area. On the basis of the requirement for avoiding the integrity risk event, the integrity parameter corrects the residual error of the corresponding correction with the 99.9% envelope probability to form the envelope, the processing method is reasonable, and the processing efficiency is high.
Owner:NO 20 RES INST OF CHINA ELECTRONICS TECH GRP

Phase locked loop with dual input reference and dynamic bandwidth control

PendingCN114640344APulse automatic controlSynchronising arrangementComputer hardwarePhase detector
Systems and methods for improved performance of phase-locked loop-based clock generators, particularly in the context of wireless audio, are disclosed herein. The PLL clock generator includes: a PLL core configured to receive a module reference clock provided by the communication module and generate a subsystem data clock corresponding to a module data clock of the communication module; and a data clock tracker module configured to receive the module data and the subsystem data clock and determine a corresponding data clock correction factor. In this way, the bandwidth of the PLL core can be dynamically changed, thereby achieving fast and very precise stabilization. The PLL core may use a low jitter frequency reference for the phase detector while using a synchronized and easily jitter audio sampling clock to ensure that the average frequency of the PLL core tracks the audio sampling clock.
Owner:SYNAPTICS INC

Clock synchronization and fault feedback method and device

PendingCN114157376ATime-division multiplexEmbedded systemClock correction
The invention provides a clock synchronization and fault feedback method, which comprises the following steps: after a slave clock receives a first message sent by a first master clock, calculating to obtain a first local clock correction value needing to be corrected by a local clock and a first maximum correction value needing to be corrected by the slave clock; after the slave clock receives a second message sent by the second master clock, calculating to obtain a second local clock correction value needing to be corrected by the local clock and a second maximum correction value needing to be corrected by the slave clock; the first local clock correction value is compared with the first maximum correction value, the second local clock correction value is compared with the second maximum correction value, and a fault identification result and a clock synchronization result of the slave clock are determined based on clock synchronization and fault identification criteria. According to the invention, whether the message sent by the master clock device is lost or has a wrong value is detected, and clock synchronization and fault positioning of the slave clock can be completed; in addition, a double-master-clock structure is adopted, so that the problem of transient failure of a single master clock is solved.
Owner:CSR ZHUZHOU ELECTRIC LOCOMOTIVE RES INST
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