4 results about "Correction code" patented technology

A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.

An error correction code of (N+M) words is configured by adding an ECC parity of M word (M is a natural number) to N words extracted at an interval of A words with respect to data of (A*N) words (A and N are natural numbers) inputted via an interface 1. A data distributor 3 distributes (N+M) words to the respective (N+M) physical blocks to record by A words. In a case where a writing error has occurred, data recorded in a cell sharing page of the page and in a page of another physical block configuring the error correction code is read. A disappearing correction is carried out to the data of the cell sharing page by using the data, and thus the data of the cell sharing page is recovered and written. In this manner, in the multi-level nonvolatile memory, an error in writing of a certain page can be prevented from propagating to a written page sharing a cell.

The invention discloses a two-dimensional code generation method and system and a document anti-counterfeiting method and system, and the method comprises the following steps: obtaining to-be-stored information, and obtaining a matched two-dimensional code template based on the to-be-stored information; generating first coded data corresponding to the two-dimensional code template based on the to-be-stored information, wherein the first coded data comprises a data code sequence and an error correction code sequence; performing interference processing on the error correction code sequence to obtain a corresponding interference sequence, and the interference sequence comprises a true error correction code and a false error correction code; and generating a corresponding two-dimensional codeon the two-dimensional code template based on the data code sequence and the interference sequence, wherein the two-dimensional code comprises a completely colored first pixel block and a partially colored second pixel block. According to the invention, by interfering the error correction code sequence and combining the design of the second pixel block, the generated two-dimensional code has certain vulnerability, pixels are easier to lose in the copying process, and unreadable copying is realized.

A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.