Nanowire MOS transistor based on III-V element and preparation method thereof

A technology of MOS transistors and nanowires, applied in the field of microelectronics, can solve the problems of increasing cost, increasing parasitic capacitance of devices, and inability to reduce channel length, etc., and achieves the effects of small contact resistance, convenient manufacture, and simple structure

Inactive Publication Date: 2010-07-21
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented technology allows for better performance by reducing electrical interference between components that are connected through an electrode on one side (the source) while still allowing them to communicate with other parts inside or outside it.

Problems solved by technology

Technological Problem: Current techniques used during production of nanoelectronics structures require thermal activation after deposition processes like sputtering, laser ablation, etching, and other treatments, leading to potential defects called dislocations and increased electrical resistivity. Additionally, current approaches involve forming sources/drains within each layer separately without overlapping them can lead to variations between layers' thickness and dopants concentration levels affecting conductive behavior.

Method used

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  • Nanowire MOS transistor based on III-V element and preparation method thereof
  • Nanowire MOS transistor based on III-V element and preparation method thereof
  • Nanowire MOS transistor based on III-V element and preparation method thereof

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Embodiment Construction

[0022] An exemplary embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, the thicknesses of layers and regions are enlarged or reduced for convenience of description, and the shown sizes do not represent actual sizes. Although these figures do not fully reflect the actual size of the device, they still completely reflect the mutual positions between the regions and the constituent structures, especially the upper-lower and adjacent relationships between the constituent structures. The referenced figures are schematic illustrations of idealized embodiments of the invention, and the illustrated embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated in the figures but are to include resulting shapes, such as manufacturing-induced deviations. For example, the curves obtained by etching are usually curved or rounded, but in the embodiment of the prese

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Abstract

The invention belongs to the technical field of micro-electronics, particularly disclosing a nanowire MOS transistor and a preparation method thereof. The nanowire MOS transistor uses metallic nickel to serve as the drain and source diffusion material of III-V semiconductor nanowire and utilizes the nickel diffusion mechanism under high temperature to ensure that metallic nickel diffuses to III-V material; formed low-resistance Ni-III-V alloy serves as the drain and source diffusion material of the III-V semiconductor nanowire MOS pipe so as to realize ohmic contact between the drain and source material and channel material. The MOS transistor disclosed by the invention has the advantages of simple structure, convenient manufacture, small contact resistance and the like, can effectively lower the possibility of producing parasitic capacitance and effectively lowers the cut-off current of the MOS transistor. Meanwhile, the invention also discloses a preparation method of the nanowire MOS transistor, can effectively control the channel length of the MOS transistor so as to ensure that a semiconductor device has larger operating current.

Description

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Claims

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Application Information

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Owner FUDAN UNIV
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