Switching noise suppression circuit integrated on A/D (analog/digital) converter chip

A technology for switching noise and suppressing circuits, applied in the field of switching noise suppressing circuits, can solve problems such as performance degradation of A/D converters, and achieve the effects of improving dynamic performance and improving compatibility

Inactive Publication Date: 2011-05-18
NO 24 RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented technology integrates an analog switch into one component called the ADI convertor (analogue signal processor). It achieves this by adding resistors or inductances along its input paths instead of just relying solely upon traditional pipelines like those described earlier. By doing these techniques, it can reduce interference between signals caused by external sources such as electromagnetic waves or other factors affecting data transmission. Overall, this design enhances overall efficiency and quality of digital communication systems.

Problems solved by technology

Technological Problem addressed in this patented study relates to improving the operation speed and precision required for advanced semiconductor analogue systems used in electronic devices like smartphones or tablets due to increasing demand for faster processing speeds and better signal quality at lower cost per bit levels compared to older designs. However, while reducing noise emissions during transmission over long distances reduces overall efficiency, resulting in reduced operability and reliance times.

Method used

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  • Switching noise suppression circuit integrated on A/D (analog/digital) converter chip
  • Switching noise suppression circuit integrated on A/D (analog/digital) converter chip
  • Switching noise suppression circuit integrated on A/D (analog/digital) converter chip

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Embodiment Construction

[0024] The specific implementation manners of the present invention are not limited to the following description, and are now further described in conjunction with the accompanying drawings.

[0025] The circuit diagram of the switching noise suppression circuit integrated on the A / D converter chip implemented by the present invention is as figure 2 shown. It consists of a positive reference pass RC network and a negative reference pass RC network.

[0026] figure 2 The specific connection relationship and functional relationship in are the same as the content of the invention in this specification, and will not be repeated here. It works like this:

[0027] Using the SSN peak model proposed by Yungseon Eo et al.:

[0028] V n max ≈ n L p β n 2

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Abstract

The invention relates to a switching noise suppression circuit integrated on an A/D (analog/digital) converter chip. The switching noise suppression circuit contains a positive reference path resistance capacitance (RC) network and a negative reference path RC network. The two RC networks are used to restrain the simultaneous switching noise (SSN) noises of the positive reference VREF+ and negative reference VREF- of an assembly line, thus the spurious free dynamic range (SFDR) of the A/D converter of a high speed high precision assembly line can be increased from 30-40dB to 80-90dB and the dynamic performance of the A/D converter of the assembly line can be greatly increased. The circuit of the invention can be widely used in the A/D converter of the high speed high precision assembly line.

Description

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Claims

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Application Information

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Owner NO 24 RES INST OF CETC
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