Semiconductor element and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as potholes, uneven dielectric layer heights, and line bending, and achieve improved floating Coupling between gates and effect of narrowing trench aspect ratio

Inactive Publication Date: 2016-10-05
WINBOND ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present in this patented technology helps reduce the size of transistors while still maintain their performance level. It involves creating sacrifices during manufacturing processes for improving device reliability or reducing defects caused by misalignments. By adding these techniques, it becomes possible to achieve smaller devices without compromising its overall quality.

Problems solved by technology

The technical problem addressed by this patented technology relates to reducing testing requirements for advanced electronic device designs while maintaining their performance at lower cost levels. Specifically, it addresses issues such as poor alignment or insufficient space fillings caused by small dimensions of interconnects that can cause electrical short circuits.

Method used

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  • Semiconductor element and manufacturing method thereof
  • Semiconductor element and manufacturing method thereof
  • Semiconductor element and manufacturing method thereof

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Embodiment Construction

[0043] Figure 1A to Figure 1F It is a schematic cross-sectional view of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

[0044] Please refer to Figure 1A Firstly, there is usually a thin film such as a gate insulating layer 102 on the surface of the substrate 100, and then stacked structures 104 have been formed on the substrate 100, wherein the aspect ratio of the grooves between the stacked structures 104 (height H1 to width W1 ratio) greater than 11, for example. When the aspect ratio of the grooves between the stacked structures 104 is greater than 11, it will be difficult to face the problem of difficult gap filling with the current technology of the present invention, and if the stacked structures 104 are conductor lines, they may also be bent under force in subsequent manufacturing processes. fold.

[0045] In this embodiment, each stack structure 104 includes, for example, a floating gate 106, an inter-gate diele

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Abstract

The invention provides a semiconductor element and a manufacturing method thereof. The manufacturing method comprises: a substrate having a plurality of stacking structures is provided, the spaces among the stacking structures are coated with fluid materials, and the parts of fluid materials are removed to form a sacrificial layer exposing the parts of stacking structures; a plurality of dielectric clearance walls are formed at the side walls of the exposed stacking structures and the sacrificial layer is removed completely; and a dielectric layer covering the stacking structures is formed on the substrate and an air clearance is formed between the two stacking structures below the dielectric clearance walls. According to the invention, a depth-width ratio of a groove is reduced and thus clearance is filled; and the air clearance for avoiding a coupling effect between gates is also formed.

Description

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Claims

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Application Information

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Owner WINBOND ELECTRONICS CORP
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