Sense amplifier for static random access memories

[0014] With reference now to FIG. 2, there is illustrated a block diagram of a static random access memory (SRAM) 20 in which a preferred embodiment of the present embodiment is applicable. Although SRAM 20 generally includes multiple columns of memory cells, only one of the columns is shown in FIG. 2 for the sake of simplicity. As shown, memory cells MC1 to MCn are coupled to a sense amplifier 21 via a multiplexor 22. Memory cells MC1 to MCn are connected between a bitline pair BL and *BL. Each of memory cells MC1 to MCn is also connected to a corresponding one of wordlines WL1 to WLn disposed in the direction perpendicular to bitline pair BL and *BL. Multiplexor 22 multiplexes all the bitline pairs of SRAM 20 into one common bitline pair cBL and *cBL.

[0015] Any one of memory cells MC1 and MCn can be selected by setting a corresponding one of wordlines WL1 to WLn to a logic high level, and holding the remaining wordlines to a logic low level. Depending on the binary data stored in th