Bolt lock device having sensing amplifier

[0020] FIG. 3 is a schematic diagram of an architecture according to an embodiment of the present invention. FIG. 4 is a signal timing diagram of the present invention.

[0021] Referring to FIG. 3 , the present invention has a latch 300 with a sense amplifier, which is applicable to a general DRAM circuit, and includes an input circuit 340, a sense amplifier 310, a latch circuit 320 and an output circuit 330 . The input circuit 340 includes a plurality of identical input units 341-34N (N≥1, N is a positive integer), wherein the number of input units depends on the needs of the application, and each input unit receives a data line signal (MDQ1- MDQN) and a complementary data line signal (MDQ1B~MDQNB), and is controlled by a data isolation signal (SAISO1~SAISON), and, at the same time, among these input units 341~34N, there is only one data input unit The isolation signal is activated (SAISO in FIG. 4 is a low voltage potential), so that the data line signal and the complemen...