5 results about "Sense amplifier" patented technology

An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.

A sense amplifier for static random access memories is disclosed. The sense amplifier includes a pair of inverters cross-coupled to each other. The sense amplifier also includes means for equalizing the charges within the pair of inverters before performing a sense operation, and means for sensing a current difference between a bitline and its complement from a memory cell during the sense operation.

The invention discloses an MRAM (Magnetic Random Access Memory) sense amplifier capable of offsetting deviation. The MRAM read-out circuit is used as a post-amplifier of the MRAM read-out circuit, andcomprises NMOS tubes M0 and M1 with the same parameters, NMOS tubes M2 and M3 with the same parameters, PMOS tubes M4 and M5 with the same parameters, capacitors C0 and C1, and three same switches K1and K2; the drain electrode of the M2 is connected with the drain electrode of the M4, wherein the connection point is a point A; the grid of M2 is connected with the grid of M4, wherein the connection point is a point B; the drain of M3 is connected with the drain of M5, wherein the connection point is a point C; the grid of M3 is connected with the grid of M5, wherein the connection point is apoint D; the capacitor C0 is connected between the point B and the point C, and the capacitor C1 is connected between the point A and the point D. In the working stage, the capacitor C0 and the capacitor C1 counteract asymmetry of the read-out differential amplifier. A pair of capacitors is added on the basis of a common differential comparator, asymmetry of the differential amplifier can be counteracted, and meanwhile the area of the amplifier does not need to be large.