3 results about "Transmission gate" patented technology

A drive circuit is provided for an OLED pixel display. The drive circuit is adapted for use with a reference voltage source. It includes a first transistor and an OLED. The output circuit of the first transistor is operably connected between the reference voltage source and the OLED. Transmission gate means responsive to a control signal are provided to transmit a data signal to the first transistor. Means are provided for controlling the first transistor in accordance with a time domain modulation signal to provide an average current to the OLED which is a function of the data signal.

The invention discloses a selector circuit with a fixed output state, relating to an integrated circuit technology. A selector comprises a transmission gate, a phase inerter and a PMOS (P-channel Metal Oxide Semiconductor) up-drawing tube. Control bits output by a control circuit are connected with the grid electrode of an NMOS (N-channel Metal Oxide Semiconductor) tube of the transmission gate and used for controlling the grid electrode of a PMOS tube of the transmission gate through the phase inverter, the grid electrode of the PMOS up-drawing tube is connected with the control bits, the source electrode of the PMOS up-drawing tube is connected with a power supply end vdd, and the drain electrode of the PMOS up-drawing tube is connected with the output end of the transmission gate. The circuit disclosed by the invention can be used for ensuring that the output end of the selector is not in an empty level state, but is drawn to the high level through the PMOS up-drawing tube when all output control bits are equal to zero, so that a static short-circuit current is prevented from being generated by a gate circuit connected with the output end; and the circuit disclosed by the invention is low in area overhead, low in requirement for parameters of the PMOS up-drawing tube, capable of reducing the amount of the control bits and eliminating the static short-circuit current, and little in influence to the performance of a chip.

The invention relates to a subthreshold latch, which comprises a master latch structure and a slave latch structure, wherein the master latch structure and the slave latch structure are provided with two input ends, namely a data input end D and a clock input end clk, and are also provided with an output end Q; the master latch consists of inverters I1, I2 and I3 and complementary metal oxide semiconductor (CMOS) transmission gates T1 and T2; the slave latch consists of inverters I4, I5 and I6 and CMOS transmission gates T3 and T4; one path of the clock input end clk is connected with an inverter I7 and is input to the master latch and the slave latch respectively, and the other path of the clock input end clk is directly input to the master latch and the slave latch; and the transmission gates are arranged in feedback loops of the master latch and the slave latch, so that the subthreshold latch can operate effectively under the condition of subthreshold. The subthreshold latch has high anti-interference capacity, and low power consumption.