Method for fabricating strained-silicon metal-oxide semiconductor transistors

Active Publication Date: 2008-08-28
MARLIN SEMICON LTD
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  • Abstract
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Benefits of technology

[0014]According to the preferred embodiment of the present invention, a second rapid thermal annealing process is specifically conducted after the formation of the epitaxial layer to improve the deactivation phenomenon caused by the baking process. It should be noted that this

Problems solved by technology

However, it has been recently pointed out that the miniaturization attained by a lithographic technology has reached its limit.
This step provides a growing surface for the epitaxial layer but also causes the dopants within the source/drain region to be gathered in the edge region of the recess, thereby inducing an uneven distribution of dopants and affecting the performance of the MOS transistor.
Secondly, after the formation of the source/drain region, a rapid thermal annealing process is conducted to

Method used

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Example

[0021]Please refer to FIGS. 7-10. FIGS. 7-10 illustrate a method of utilizing selective epitaxial growth process for fabricating a strained-silicon metal-oxide semiconductor transistor according to the preferred embodiment of the present invention. As shown in FIG. 7, a semiconductor substrate 40, such as a silicon substrate is first provided. The semiconductor substrate 40 includes a gate structure 42 thereon, in which the gate structure 42 includes a gate dielectric 44 and a gate 46 disposed on the gate dielectric 44. An ion implantation process is performed thereafter to inject a p-type or n-type dopant of smaller concentration into the semiconductor substrate 40. The implantation process preferably forms a lightly doped drain 54 in the semiconductor substrate 40 surrounding the gate structure 42. An offset spacer 48 is formed on the sidewall of the gate structure 42 and a spacer 50 is formed around the offset spacer 48 thereafter. Preferably, the gate dielectric 44 is composed insu

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Abstract

A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

Description

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Claims

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Application Information

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Owner MARLIN SEMICON LTD
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