Non-volatile memory storage device and operation method thereof

[0020]Embodiments of the present invention will now be described with reference to the accompanying drawings. A flash memory device is exemplified but not limited for non-volatile memory of the present invention below.

[0021]FIG. 8 illustrates a 64-bit flash memory storage device 50 having a flash controller 51 and a flash memory 52. The flash memory 52 is a memory array of flash memory chips 54. The flash controller 51 includes Flash Control Circuit 0, Flash Control Circuit 1, Flash Control Circuit 2 and Flash Control Circuit 3. Chip-enable signals CE[0], CE[1], . . . , CE[15] each control the flash memory chips 54 of the flash memory 52 in the same column. Flash data bus FD[15:0] is between the Flash Control Circuit 0 and the flash memory chips 54 of the first two rows. Flash data bus FD[31:16] is between the Flash Control Circuit 1 and the flash memory chips 54 of the third and fourth rows. Data bus FD[47:32] is between the Flash Control Circuit 2 and the flash memory chips 54 of the