Electrolyte pattern and method for manufacturing an electrolyte pattern

Inactive Publication Date: 2009-02-12
SEIKO EPSON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0039]Due to the use of a gel electrolyte pattern and the presence of the bank layer in the transistor described above, the risk of the electrolyte leaking and causing damage to other nearby components is greatly reduced. The use of a gel electrolyte pattern also allows other layers such as a gate electrode to be deposited on top of the electrolyte layer without the risk of creating short circuits with the semiconductor in the transistor channel. In addition, since the transistor structure of the present invention has a gel electrolyte layer confined to a window in a bank layer, i.e. a gel electrolyte

Problems solved by technology

A major disadvantage of ECTs is the fact that, in comparison to OFETs, their switching times are very long.
Two major problems with electrolyte-gated transistors are their low operation frequencies and the occurrence of hysteresis during switching.
In the case of ECTs, an additional factor limiting the switching speed is the rate of diffusion of counter-ions into the bulk of the semiconductor material in the transistor channel.
A contributing factor to the occurrence of hysteresis during switching of both electrolyte-gated FETs and ECTs is the transient inhomogeneity of the electric field along the width of the transistor channel when a laterally positioned gate electrode is used.
Another problem with electrolyte-gated transistors is the leakage and diffusion of ions from the electrolyte into other device components.
The performance of electric field-driven devices

Method used

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Examples

Experimental program
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Example

EXAMPLE

[0147]The following is a preferred embodiment of the manufacturing method and the resulting transistor according to the present invention. In a first step, source, drain, and gate electrodes are patterned from an evaporated gold layer on a glass substrate. The source and drain electrodes are separated so as to define a transistor channel between them. The channel length L is 20 μm, and the width W is 1 mm. The gate electrode is positioned laterally to the source-drain electrode pair, at a distance of 1 mm.

[0148]A thin layer (40 nm thick) of the semiconducting polymer ADS2008 (supplied by American Dye Source Inc., Canada) is then spin-coated onto the substrate from a 1% toluene solution and annealed in air. Annealing is performed at a temperature of 80 deg. C. for 10 minutes.

[0149]A layer (600 nm thick) of the gelling agent poly(methylmethacrylate) (PMMA) is spin-coated onto the semiconductor layer from a 6% butylacetate solution and annealed in air. Again, annealing is performed

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PUM

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Abstract

A method for manufacturing a gel electrolyte pattern is disclosed, the method comprising depositing an electrolyte precursor by inkjet printing onto a gelling agent layer. A gel electrolyte pattern is also disclosed, the gel electrolyte pattern comprising either a mixture of a gelling agent and an electrolyte precursor or the products of a chemical reaction between a gelling agent and an electrolyte precursor.

Description

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Claims

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Application Information

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Owner SEIKO EPSON CORP
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